In general, a conventional semiconductor memory device such as a dynamic random access memory (DRAM) is becoming faster and more integrated according to a user's requirements. A DRAM may include an access transistor and a storage capacitor as a unit memory cell. The conventional DRAM is generally employed as a main memory device in an electronic system.
For example, when memory cells integrated in a memory cell array region have a defect, the defective memory cell or cells cannot serve as a storage device in a read or write operation. Furthermore, manufacturing all memory cells designed through semiconductor manufacturing processes without defects may be difficult. Therefore, manufacturers of semiconductors install redundancy memory cells besides normal memory cells so that defective cells may be replaced with redundancy memory cells when normal memory cells are defective.
To obtain a redundancy scheme, a test such as a parallel bit test or multibit test may be used to decide which cell has a defect among normal memory cells.
The parallel bit test may be performed in an electrical die sorting (EDS) process, in which a shortened test time is preferred. Therefore, the parallel bit test may used instead of a serial bit test. A parallel bit test (PBT) of related art and an enhanced parallel bit test (ePBT) are described referring to FIGS. 1 to 5.
A general DRAM employs a parallel bit test circuit to perform a parallel test of a plurality of bits. In a parallel bit test mode, same data are written to N memory cells, N being a natural number of 2 or more, and then data of N bits are simultaneously read. The read data of N bits are compared to each other by a comparator. An output from the comparator indicates whether the bits are equal (e.g., “pass”) or are unequal (e.g., “fail). Depending on the equal or unequal result, a “1”/“0” is output as test result data. In the parallel bit test mode, the number of cycles to test all bits is reduced to 1/N and thus the test time can be shortened.
FIG. 1 illustrates a test block for a semiconductor memory device. In a configuration of FIG. 1, an input mode selector 100 transfers input data DI to a plurality of cell arrays 200 by selecting one of a normal mode and a test mode. In the normal mode, the input mode selector 100 transfers the input data D1 to one of the plurality of cell arrays 200. In the test mode, the input mode selector 100 transfers the input data D1 to all of the plurality of cell arrays 200. The plurality of cell arrays 200 stores the input data and output data to a comparator 300. The comparator 300 generates a comparison output signal com_out by comparing outputs of the plurality of cell arrays 200. An output mode selector 400 selects a mode (e.g., test or normal) in an output terminal and outputs a test result or data DQ to the outside according to the selected mode. For example, if the normal mode is selected, an output from one of the plurality of cell arrays 200 is selected.
In a normal mode of FIG. 1, one word line and bit lines corresponding to the number of input/output bits within one of the plurality of cell arrays 200 are selected through a combination of a row address and a column address to access a cell in the same scheme as an operation of general memory. Therefore, data of cells are written or read.
In a parallel bit test mode, the input mode selector 100 selects the test mode and the same data is written to the plurality of cell arrays 200. Data that is output from each of the plurality of cell arrays 200 are applied to the comparator 300 through a sense amplifier in a read operation for the test. When the data output from each of the plurality of cell arrays 200 are all ‘low’ or all ‘high’, the output com_out of the comparator is a ‘low’ level. When the data input to the comparator 300 differs, the output com_out becomes a ‘high’ level. The output com_out are buffered and transferred to the output terminal through the output mode selector 400.
For example, when data of four cell arrays of the plurality of cell arrays 200 are all the same, it is decided the test result is normal and thus an output data DQ is output as a logic ‘low’ level. However, when one or more of data of the four cell arrays of the plurality of cell arrays 200 are different from one another, the output data DQ is output as logic ‘high’ as an error in the test result.
FIGS. 2 and 3 are examples of a general test circuit. FIG. 4 is a circuit diagram of a comparator illustrated in FIG. 2. FIG. 5 illustrates an example data input/output control in a general parallel bit test.
An example of parallel bit test (hereafter, referred to as “PBT”) for use in a semiconductor memory device is described as follows.
In FIG. 2, during a test mode, a memory cell array 10 outputs first through fourth memory cell data D0-D3. The first memory cell data D0 are applied to a first input/output sense amplifier 20, and the second memory cell data D1 is applied to a second input/output sense amplifier 22. Furthermore, the third memory cell data D2 is applied to a third input/output sense amplifier 21 and the fourth memory cell data D3 is applied to a fourth input/output sense amplifier 23. For example, when in a PBT mode, the first to fourth input/output sense amplifiers 20 to 23 may individually output data of 0, 1, 0, 0 through a sense amplification operation, a comparison output of a first comparator 30 is provided as a fail because the first memory cell data D0 is faulty. As shown in FIG. 2, the first memory cell data D0 is not the correct data. The second comparator 32 outputs a pass signal. The first and second comparators 30 and 32 individually output a pass signal when data of two input terminals are applied in a mutually equal logic level. An output DQ0 of a third comparator 40 receiving the outputs of the first and second comparators 30 and 32 is provided as a fail when the outputs of the first and second comparators 30 and 32 are not equal.
FIG. 3, illustrates an enhanced parallel bit test (hereafter, referred to as “ePBT”) of a semiconductor memory device.
In FIG. 3, during a test mode, the memory cell array 10 outputs the first through fourth memory cell data D0-D3. The first memory cell data D0 is applied to first input/output sense amplifier 20. As shown in FIG. 3, the first memory cell data D0 should be a one, but because of the faulty cell, a zero is output. The second memory cell data D1 is applied to second input/output sense amplifier 22. Furthermore, the third memory cell data D2 are applied to third input/output sense amplifier 21 and the fourth memory cell data D3 are applied to fourth input/output sense amplifier 23. For example, when in a PBT mode, the first to fourth input/output sense amplifiers 20-23 individually output data of 0, 1, 0 and 0 through a sense amplification operation. Expected data applied from a tester are respectively input as 1, 1, 0 and 0 to the first to fourth comparators 30-33. Accordingly, a comparison output of the first comparator 30 is provided as a fail, and comparison outputs of second to fourth comparators 31-33 are all provided as pass signals. The first to fourth comparators 30-33 all perform an exclusive OR (XOR_gating operation). Outputs of the first to fourth comparators 30-33 are gated through a fifth comparator 41 and output provided as the output data DQ0. The first to fourth comparators 30-33 of FIG. 3 may be respectively realized as a circuit device including MOS transistors as shown in FIG. 4.
FIG. 4 illustrates an example embodiment of the first comparator 30. The second to fourth comparators 31-33 have the same circuit configuration. For the sake of clarity and brevity, a detailed description of the second to fourth comparators 31-33 will be omitted. FDOI indicates an output of the input/output sense amplifier 20, and WDI denotes the expected data applied from the tester. When values of FDOI and WDI are the same, a low level (e.g., “0”) is provided in an output node NO1 and output as comparison output data DOUT. When the values of FDOI and WDI are different from each other, a first value (e.g., “1”) is provided in an output node NO1.
However, in the examples of PBT and ePBT shown in FIGS. 2 and 3, the memory cell outputting D0 may be decided as a failed cell even though the D0 memory cell is non-defective. More specifically, when a charge is discharged to a cell coupled to the same word line, the memory cell may be determined as defective. In other words, when a bridge occurs between adjacent memory cells using different bit lines but sharing the same word line, a discharge of cell data occurs, and the D0 memory cell should output data ‘1’ but actually outputs data ‘0’. Such an error may occur in performing a parallel bit test by executing a data read after a data write and a lapse of given time, for example. As a result, when the read for the D0 memory cell is performed after a lapse of given time, a charge level of the D0 memory cell is discharged to a D1 memory cell and thus, the cell becomes a low level. Then, an output of the bit line sense amplifier 20 is provided as ‘0’ and then the D0 memory cell is decided as a defective memory cell despite that the cell is a normal memory cell.
When the error occurs in the decision to determine a defective cell like in FIGS. 2 and 3, a normal memory cell is decided as a defective cell in the PBT/ePBT and screened, thus causing an overkill of memory cells and lowering a production yield. A yield drop is relatively severe like in process products having a relatively low design rule, thus, the PBT/ePBT are difficult to be applied thereto. Furthermore, in performing the test by using a normal mode, the occurrence of overkill can be prevented, but a test time increases to 4-16 times as compared with PBT.
On the other hand, as shown in FIG. 5, DQ transmission gates 24-29, 34 and 36 may be added between the sense amplifiers 20-23 and the comparators 30 and 32 for a parallel bit test. For example, when a mode control signal MOD0 is applied as a low state to the transistors 24 and 25, an output of the first input/output sense amplifier 20 is blocked and a first expected data WD0 is output to one input of the comparator 30. Therefore, an output of the first comparator 30 is provided as the pass, thereby preventing an overkill for the memory cell D0.
However, the transmission gates 24-29, 34 and 36 cause a relatively large occupation rate within the circuit. Therefore, circuit design of the semiconductor memory device becomes a burden.
However, when an error in a fail decision of a memory cell occurs in the parallel bit test, an overkill operation of the memory cell may be generated and, thus, a production yield may decrease. Furthermore, a control circuit logic is added to a normal path to perform the parallel bit test. The control circuit logic maybe difficult to realize and influence the normal path.